A flash memory is a kind of a programmable ROM (PROM) in which data can be electrically erased or programmed. Flash memory combines advantages of an erasable PROM (EPROM) and an electrically erasable PROM (EEPROM). An EPROM includes a memory cell with one transistor to provide a small cell area, but it must be erased by ultraviolet rays. An EEPROM includes a memory cell with two transistors which is electrically erasable, but it requires a large cell area. A flash memory includes one transistor like the EPROM, while retaining the electrical erasing capability of the EEPROM. Flash memory is perhaps more correctly referred to as a flash EEPROM.
According to the structure of a cell array, flash memory may be classified as having a NOR-type structure, in which cells are arranged in parallel between a bit line and the ground, or as having a NAND-type structure, in which the cells are arranged in series between the bit line and the ground. Since the NOR-type flash memory, with a parallel structure, supports high-speed random access in reading, the NOR-type flash memory may be used for booting portable phones. Since the NAND-type flash memory, having a series structure, has a fast writing speed and a low reading speed, the NAND-type flash memory is suitable for data storage and applications where compactness is especially important.
Flash memory may also be classified into stack gate types and split gate types according to the structure of a unit cell. Further, flash memory devices can be classified as floating gate devices and silicon-oxide-nitride-oxide-silicon (SONOS) devices according to the type of charge storage layer employed. Floating gate devices include a floating gate of polycrystalline silicon surrounded by an insulator. Charges are injected into or emitted from the floating gate by channel hot carrier injection or Fowler-Nordheim tunneling (F-N tunneling), to store or erase data.
According to a related method of manufacturing flash memory devices, to form a cell junction, an ion implantation process for a recess common source (RCS) region connecting sources of several cells, and a cell source/drain (CSD) ion implantation process of forming a source/drain junction before forming spacers of a gate are performed. In other words, an ion implantation process of forming the junction between cells includes the ion implantation process for the RCS region after the RCS region has been formed and the CSD ion implantation process performed after the ion implantation process for the RCS region. Therefore, to perform the CSD ion implantation process after the RCS region has been formed and then the ion implantation process has been performed with respect to the RCS region, pattering, ion implantation, ashing, and cleaning must be repeated twice.